A high-output semiconductor power amplifier employing an MMIC technique conventionally includes: dividers configured to divide an input signal; an amplifier configured by connecting a plurality of unit FETs (FET: Field Effect Transistor) in parallel at a plurality of stages; and combiners configured to combine the outputs from the amplifier and output the resultant signal. The amplifier of this type can achieve a high amplification factor and a high output while maintaining a fine linearity. The high-output semiconductor power amplifier generally uses unit FETs with a multi-finger structure to fulfill the need for a wide gate width (see the U.S. Pat. No. 5,111,157, for example).
The multi-stage high-output amplifiers using the unit FETs with the multi-finger structure are increased in chip size with increase in the number of unit FETs disposed in parallel for achieving a large output. Specifically the chip size increases due to large regions occupied by the unit FETs and regions occupied by the dividers, combiners, and impedance matching circuits disposed between the stages.
To achieve a small chip size, small via holes are formed respectively on the source electrodes of each unit FET, for example. Alternatively, via holes are shared by a plurality of unit FETs to decrease the number of via holes. Decreasing the number of via holes, however, increases the ground inductance and also causes variations in gain among the unit FETs, hence leading to a poor balance of the amplifier as a whole. Thus, high-output amplifiers have a problem that loop oscillation is likely to occur.